Starting from 20 nm technology node, more and more high-end chips are packaged with flip chip in order to reduce their size and increase IOs. Backside FIB circuit edit (CE) is then needed. Different from the traditional FIB CE (front-side), backside FIB CE is much challenging. It will start from Si substrate and penetrate the most sensitive/critical area, such as dopant well (P-well or N-well), STI, PMOS, NMOS, and M0. Any remiss edits will cause IC failure. How to plan FIB CE in advance, precise edit, control damage area and protection is crucial for the backside FIB CE.
Figure 1. Figure a: The cartoon of the backside FIB CE. The plan is connecting M2 with M3. Figure b: Backside FIB CE image (20 nm technology node). The size of the Si trench is about 350㎛ x 350㎛ and 260㎛ in depth. Precise FIB CE will then start after the Si trench. In order to easily measure signal, external wires can be combined with FIB CE.
【Case ②】12 nm backside FIB CE
Figure 2. The FIB CE plan is 1 line + 1 cut (12 nm technology node). The opening window for CE is limited, only 0.15 ㎛ x 0.15㎛. The expected yield is 0 % by one of service labs and 50 % by MSS. In the end, the MSS backside FIB CE is successful. Figure a exhibits two CE windows, one for connection and the other one for cut (already cut and the beneath via can be seen). Figure b exhibits the final image.
【Case ③】40 nm backside FIB CE
Figure 3. The challenging of this backside FIB CE is two CE plans needed to be conducted in the same die (40 nm technology node) and the separation between these two plans is about 280㎛, which is very close to the maximum window for the backside FIB CE (about 350㎛ x 350㎛). The expected yield is 50 % by one of service labs. MSS conducted the job successfully. Figure a exhibits two windows for FIB CE. The target layer is at M7, the top metal layer. The thickness of the line is 5 ㎛ in order to carry higher current (max. 5 mA). Figure b exhibits the final image.